# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_IMXRT10XX
	select CPU_CORTEX_M7
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE
	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
	select ARM
	select CLOCK_CONTROL
	select HAS_MCUX
	select HAS_MCUX_CACHE
	select HAS_MCUX_CCM if !SOC_MIMXRT1042
	select HAS_MCUX_FLEXSPI
	select HAS_MCUX_IGPIO
	select HAS_MCUX_LPI2C if !SOC_MIMXRT1042
	select HAS_MCUX_LPSPI if !SOC_MIMXRT1042
	select HAS_MCUX_LPUART if !SOC_MIMXRT1042
	select HAS_MCUX_GPT if !SOC_MIMXRT1042
	select HAS_MCUX_TRNG if !SOC_MIMXRT1042
	select HAS_MCUX_EDMA
	select HAS_MCUX_GPC
	select HAS_MCUX_IOMUXC
	select HAS_MCUX_PMU
	select HAS_MCUX_DCDC
	select HAS_MCUX_USB_EHCI
	select HAS_SWO
	select HAS_PM
	select SOC_RESET_HOOK
	select SOC_EARLY_INIT_HOOK

config SOC_MIMXRT1011
	select CPU_HAS_FPU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_ICACHE
	select CPU_HAS_DCACHE

config SOC_MIMXRT1015
	select CPU_HAS_FPU
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU

config SOC_MIMXRT1021
	select HAS_MCUX_ENET
	select HAS_MCUX_SEMC
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_FLEXCAN
	select HAS_MCUX_PWM

config SOC_MIMXRT1024
	select HAS_MCUX_ENET
	select HAS_MCUX_SEMC
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_FLEXCAN
	select HAS_MCUX_SRC

config SOC_MIMXRT1042
	select HAS_MCUX_SEMC
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU

config SOC_MIMXRT1052
	select HAS_MCUX_ELCDIF
	select HAS_MCUX_ENET
	select HAS_MCUX_SEMC
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_FLEXCAN
	select HAS_MCUX_PWM
	select HAS_MCUX_SRC

config SOC_MIMXRT1062
	select HAS_MCUX_ELCDIF
	select HAS_MCUX_ENET
	select HAS_MCUX_PWM
	select HAS_MCUX_QTMR
	select HAS_MCUX_SEMC
	select HAS_MCUX_SNVS
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_FLEXCAN
	select HAS_MCUX_I2S
	select HAS_MCUX_ADC_ETC
	select HAS_MCUX_SRC

config SOC_MIMXRT1064
	select HAS_MCUX_ELCDIF
	select HAS_MCUX_ENET
	select HAS_MCUX_PWM
	select HAS_MCUX_QTMR
	select HAS_MCUX_SEMC
	select HAS_MCUX_SNVS
	select HAS_MCUX_SRC
	select CPU_HAS_FPU_DOUBLE_PRECISION
	select CPU_HAS_ARM_MPU
	select HAS_MCUX_USDHC1
	select HAS_MCUX_USDHC2
	select HAS_MCUX_FLEXCAN
	select HAS_SWO

if SOC_SERIES_IMXRT10XX

config INIT_ENET_PLL
	bool "Initialize ENET PLL"
	default y if ETH_NXP_ENET
	help
	  When enabled, will call the SDK function to initialize the enet pll.
	  The exact meaning of what the "enet pll" is in the hardware according
	  to the SDK changes per platform, and so does the API signature.
	  This configuration also assumes a certain default clocking scheme for each SOC.
	  See soc.c code and HAL fsl_clock.c for the platform for better understanding.

config INIT_PLL6_500M
	bool "PLL6 500M output enable"
	default y
	depends on SOC_MIMXRT1011 || SOC_MIMXRT1015 || \
		   SOC_MIMXRT1021 || SOC_MIMXRT1024
	select INIT_ENET_PLL

config INIT_SYS_PLL
	bool "Initialize System PLL"
	default y if SOC_MIMXRT1042

config INIT_VIDEO_PLL
	default y if DISPLAY_MCUX_ELCDIF
	depends on !SOC_MIMXRT1011 && !SOC_MIMXRT1015 && \
		   !SOC_MIMXRT1021 && !SOC_MIMXRT1024

endif # SOC_SERIES_IMXRT10XX
