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cmd": {}}}, "diff_num": 12}, "less": {"less_details": {}, "less_num": 0}, "more": {"more_details": {}, "more_num": 0}}, "pr_link": "https://gitcode.com/src-openeuler/qemu/pull/1308", "pr_changelog": "* Wed May 20 2026 Pengrui Zhang <zhangpengrui@huawei.com> - 11:8.2.0-76\n- hw/core/machine-smp: Deprecate unsupported \"parameter=1\" SMP configurations\n- hw/core/machine-smp: Calculate total CPUs once in machine_parse_smp_config()\n- hw/core/machine: Introduce the module as a CPU topology level\n- hw/core/machine: Support modules in -smp\n- hw/core: Introduce module-id as the topology subindex\n- hw/core: Support module-id in numa configuration\n- hw/i386: split x86.c in multiple parts\n- i386/cpu: Fix i/d-cache topology to core level for Intel CPU\n- i386/cpu: Use APIC ID info to encode cache topo in CPUID[4]\n- i386/cpu: Use APIC ID info get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14]\n- i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid()\n- i386/cpu: Introduce bitmap to cache available CPU topology levels\n- i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB]\n- i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level\n- i386: Introduce module level cpu topology to CPUX86State\n- i386: Support modules_per_die in X86CPUTopoInfo\n- i386: Expose module level in CPUID[0x1F]\n- i386: Support module_id in X86CPUTopoIDs\n- i386/cpu: Introduce module-id to X86CPU\n- tests: Add test case of APIC ID for module level parsing\n- hw/i386/pc: Support smp.modules for x86 PC machine\n- i386: Add cache topology info in CPUCacheInfo\n- i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4]\n- i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]\n- i386: Add support for SUCCOR feature\n- i386/cpu: fixup number of addressable IDs for processor cores in the physical package\n- kvm: Allow kvm_arch_get/put_registers to accept Error**\n- i386/cpu: Don't enumerate the \"invalid\" CPU topology level\n- hw/core: Make CPU topology enumeration arch-agnostic\n- qapi/qom: Define cache enumeration and properties for machine\n- hw/core: Check smp cache topology support for machine\n- hw/core: Add a helper to check the cache topology level\n- hw/core/machine-smp: Initialize caches_bitmap before reading\n- hw/core/machine-smp: Fix error message parameter\n- i386/cpu: Extract a common fucntion to setup value of MSR_CORE_THREAD_COUNT\n- i386/cpu: Drop the variable smp_cores and smp_threads in x86_cpu_pre_plug()\n- i386/cpu: Drop cores_per_pkg in cpu_x86_cpuid()\n- i386/topology: Update the comment of x86_apicid_from_topo_ids()\n- i386/topology: Introduce helpers for various topology info of different level\n- target/i386/cpu: Consolidate the use of warn_report_once()\n- i386/cpu: Track a X86CPUTopoInfo directly in CPUX86State\n- i386/cpu: Hoist check of CPUID_EXT3_TOPOEXT against threads_per_core\n- cpu: Remove nr_cores from struct CPUState\n- i386/cpu: Set up CPUID_HT in x86_cpu_expand_features() instead of cpu_x86_cpuid()\n- i386/cpu: Set and track CPUID_EXT3_CMP_LEG in env->features[FEAT_8000_0001_ECX]\n- hw/core/machine: Reject thread level cache\n- i386/cpu: Support module level cache topology\n- i386/cpu: Update cache topology with machine's configuration\n- i386/pc: Support cache topology in -machine for PC machine\n- i386/cpu: add has_caches flag to check smp_cache configuration\n- i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f\n- i386/cpu: Move adjustment of CPUID_EXT_PDCM before feature_dependencies[] check\n- i386/cpu: Rename enable_cpuid_0x1f to force_cpuid_0x1f\n- i386/cpu: Refine comment of CPUID2CacheDescriptorInfo\n- i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding\n- i386/cpu: Add default cache model for Intel CPUs with level < 4\n- i386/cpu: Present same cache model in CPUID 0x2 & 0x4\n- i386/cpu: Consolidate CPUID 0x4 leaf\n- i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState\n- i386/cpu: Add x-vendor-cpuid-only-v2 option for compatibility\n- i386/cpu: Mark CPUID[0x80000005] as reserved for Intel\n- i386/cpu: Rename AMD_ENC_ASSOC to X86_ENC_ASSOC\n- i386/cpu: Fix CPUID[0x80000006] for Intel CPU\n- i386/cpu: Add legacy_intel_cache_info cache model\n- i386/cpu: Add legacy_amd_cache_info cache model\n- i386/cpu: Select legacy cache model based on vendor in CPUID 0x2\n- i386/cpu: Select legacy cache model based on vendor in CPUID 0x4\n- i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005\n- i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006\n- i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D\n- i386/cpu: Use a unified cache_info in X86CPUState\n- i386/cpu: Introduce cache model for SierraForest\n- i386/cpu: Introduce cache model for GraniteRapids\n- i386/cpu: Introduce cache model for SapphireRapids\n- i386/cpu: Add a \"x-force-cpuid-0x1f\" property\n- i386/cpu: Enable 0x1f leaf for SierraForest by default\n- i386/cpu: Enable 0x1f leaf for SierraForest by default\n- i386/cpu: Enable 0x1f leaf for GraniteRapids by default\n- i386/cpu: Enable 0x1f leaf for SapphireRapids by default\n- i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel\n- i386/cpu: Mark CPUID 0x80000007[EBX] as reserved for Intel\n- i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin\n- i386/cpu: Reorder CPUID leaves in cpu_x86_cpuid()\n- i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16]\n- i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16]\n- i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14]\n- hw/core: allow parameter=1 for SMP topology on any machine\n- docs/deprecated: Remove undeprecated SMP description\n- i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported\n- i386/hvf: Make CPUID_HT supported\n- target/i386/cpu: Move addressable ID encoding out of compat property in CPUID[0x1]\n- target/i386: add compatibility property for pdcm feature\n"}